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Microprocessor: CPU only. Needs external memory and peripherals.

Microcontroller: CPU + memory + peripherals in one chip.

📘 Formal Definition (8051 Microcontroller)

The 8051 microcontroller is an 8-bit microcontroller developed by Intel, widely used in embedded systems. It includes a CPU, RAM, ROM, I/O ports, timers, serial communication, and interrupt control, all integrated on a single chip, making it suitable for control-oriented embedded applications.

🔍 Features of 8051 Microcontroller (as per CS3691):

8-bit processor: Can process 8 bits of data at a time.
Clock speed: Typically 12 MHz.
Memory:
- 4 KB on-chip ROM (program memory)
- 128 bytes on-chip RAM (data memory)
I/O Ports: 4 parallel I/O ports (each 8-bit) – total 32 I/O lines.
Timers: Two 16-bit timers/counters (Timer 0 and Timer 1).
Interrupts: 5 interrupt sources.
Serial Communication: One full-duplex UART.
On-chip oscillator and clock circuitry.
Harvard Architecture: Separate memory for program and data.
Bit as well as byte addressable RAM.

🧠 Introduction to 8051 Architecture

The 8051 is an 8-bit microcontroller with a Harvard architecture. It integrates a CPU, RAM, ROM, I/O ports, timers, serial communication, and interrupt control—ideal for embedded control applications.

🧩 Block Diagram Overview

The block diagram typically includes:

CPU (with ALU and registers)
4 I/O Ports (P0–P3)
Program Memory (ROM)
Data Memory (RAM)
Timers/Counters (T0, T1)
Serial Port (TxD, RxD)
Interrupt Control
Oscillator & Clock Circuit
Internal Buses

🧬 Internal Components Overview

CPU (Central Processing Unit)
ALU (Arithmetic and Logic Unit)
Registers (A, B, PSW, SP, PC, DPTR)
ROM (4KB) and RAM (128B)
Timers – T0 and T1
Serial port
Interrupt system
Oscillator and clock

🧮 Central Processing Unit (CPU)

Coordinates all operations: fetching, decoding, executing instructions.

➕ Arithmetic and Logic Unit (ALU)

Performs arithmetic (add, subtract) and logical (AND, OR, etc.) operations.

🧾 CPU Registers Overview

🅰️ Register A (Accumulator)

Primary register for arithmetic, logic, and data movement.

🅱️ Register B

Used during multiplication/division and temporary storage.

🔢 Data Pointer (DPTR)

16-bit: split into DPH (high byte) and DPL (low byte); used to access external memory.

📍 Program Counter (PC)

16-bit; points to the next instruction to execute.

🔁 Stack Pointer (SP)

8-bit; points to the top of the stack (default value: 07H).

🏁 Flag Register & PSW (Program Status Word)

🏳️ Flag Bits:

CY – Carry
AC – Auxiliary Carry
F0 – User-defined
RS1, RS0 – Register bank select
OV – Overflow
P – Parity

🧩 PSW Bit Pattern:

text
CY | AC | F0 | RS1 | RS0 | OV | — | P

🗃️ Register Bank Selection:

RS1 RS0 = 00 → Bank 0
RS1 RS0 = 01 → Bank 1
RS1 RS0 = 10 → Bank 2
RS1 RS0 = 11 → Bank 3

🧠 Memory Organization

📂 Data Memory (RAM)

128 Bytes Internal RAM:
- 00H–1FH: Working registers
- 20H–2FH: Bit-addressable
- 30H–7FH: General purpose

📄 Program Memory (ROM)

4KB internal ROM for code storage

🔄 Memory Mapping and Bus

Harvard architecture (separate buses)
Internal data bus for internal transfers

🖧 I/O Ports

🔌 4 x 8-bit Ports

P0: Dual role (I/O & address/data lines for external memory)
P1: General-purpose I/O
P2: Used for high-order address in external memory
P3: Alternate functions (RxD, TxD, INT, T0, T1)

📍 Bit/Byte Addressing

Some ports are bit-addressable (e.g., P1.0, P1.1...)

📋 Special Function Registers (SFRs)

🛠️ Definition:

Registers that control functions (e.g., timers, serial, I/O).

📊 SFR Address Range: 80H–FFH

🔘 Bit-addressable SFRs:

Accumulator (A), B register, PSW, Ports (P0–P3), IE, IP, etc.

⏱️ Timers and Counters

⌚ Timer 0 & Timer 1

16-bit each
Modes: 13-bit, 16-bit, 8-bit auto-reload

⚙️ Control Registers

TCON: Timer control
TMOD: Mode control

📨 Serial Communication

🔁 Serial Port:

TxD (transmit), RxD (receive)

📡 Control Registers:

SCON – Serial Control
SBUF – Serial data buffer

🚨 Interrupt System

⚡ Sources:

INT0, INT1 (external)
T0, T1 (timers)
Serial port

🧭 SFRs for Interrupts:

IE (Interrupt Enable)
IP (Interrupt Priority)

⏲️ Oscillator and Clock

Frequency Range: 4–30 MHz (standard: 12 MHz)
Uses external crystal oscillator

🔗 Bus System

🚌 Internal Bus:

Transfers data between CPU and internal components.

🔌 External Bus:

For interfacing with external memory/peripherals.

📘 8051 Microcontroller: Pin Description — Topics & Subtopics

🔷 1. 8051 Pin Overview

Total of 40 pins
Packaged in a 40-pin Dual Inline Package (DIP)
Some pins have multiplexed or alternate functions

🔷 2. I/O Ports (32 pins total)

✅ Port 0 (Pins 32–39)

Dual function:
- General-purpose I/O
- Time-multiplexed Address/Data bus (AD0–AD7) for external memory
Requires external pull-up resistors for I/O operations

✅ Port 1 (Pins 1–8)

General-purpose I/O only
Not multiplexed
Internally pulled up

✅ Port 2 (Pins 21–28)

High-order address lines (A8–A15) during external memory access
Acts as general-purpose I/O when external memory is not used

✅ Port 3 (Pins 10–17)

Multifunctional port: I/O + alternate functions

🔁 Port 3 Alternate Functions

Pin	Name	Alternate Function
10	P3.0	RXD – Serial input
11	P3.1	TXD – Serial output
12	P3.2	INT0 – External interrupt 0
13	P3.3	INT1 – External interrupt 1
14	P3.4	T0 – Timer 0 input
15	P3.5	T1 – Timer 1 input
16	P3.6	WR – Write signal for external memory
17	P3.7	RD – Read signal for external memory

🔷 3. Power Supply Pins

Pin	Name	Description
40	Vcc	+5V DC power supply
20	Vss	Ground

🔷 4. Oscillator Pins

Pin	Name	Function
19	XTAL1	Input to internal oscillator (from crystal)
18	XTAL2	Output from internal oscillator

Typically connected to a 12 MHz crystal

🔷 5. Control and Special Function Pins

Pin	Name	Description
9	RST	Reset input (active HIGH) – resets microcontroller
30	ALE	Address Latch Enable – de-multiplexes address/data from Port 0
29	PSEN	Program Store Enable – read strobe for external program memory
31	EA	External Access – low: external ROM, high: internal ROM

🔷 1. Total Accessible Memory Range

Type of Memory	Size	Address Range
Program Memory	64 KB	0000H – FFFFH
Data Memory	64 KB	0000H – FFFFH

🔷 2. Internal Memory Capacities

Memory Type	Size
Internal ROM (Program)	4 KB
Internal RAM (Data)	256 bytes

📄 3. Program Memory (ROM/EPROM)

✅ Internal Program Memory

Size: 4KB
Address Range: 0000H – 0FFFH
Stores program instructions
Accessed when EA pin is HIGH

✅ External Program Memory

Size: Up to 64KB
Address Range: 0000H – FFFFH
Accessed when EA pin is LOW
PSEN signal is used to enable external ROM

🔌 4. EA (External Access) Pin Functionality

EA Pin	Function
EA = 1	Use internal 4KB ROM
EA = 0	Access full external ROM (up to 64KB)

📦 5. Data Memory (RAM)

✅ Internal RAM (256 bytes total)

Split into two parts:

Range	Access Type	Description
00H – 7FH	Direct & Indirect	Lower 128 bytes
80H – FFH	Indirect only	Upper 128 bytes – SFR area

🔍 6. Internal RAM Organization (00H–7FH)

Range	Section	Details
00H–1FH	Register Banks	4 banks × 8 registers (R0–R7)
20H–2FH	Bit Addressable Area	16 bytes → 128 addressable bits
30H–7FH	General Purpose RAM	For variables, temporary data, stack

🗂️ 7. Register Banks (00H–1FH)

Bank	PSW Bits RS1 RS0	Address Range
Bank 0	00	00H–07H
Bank 1	01	08H–0FH
Bank 2	10	10H–17H
Bank 3	11	18H–1FH

➡️ Selected using RS1 and RS0 bits in PSW register

🎯 8. Bit Addressable Area (20H–2FH)

16 bytes → 128 bits (bit addresses: 00H – 7FH)
Each byte has 8 bits that can be accessed individually
Useful for flags, control bits, etc.

📌 9. General Purpose RAM (30H–7FH)

80 bytes of RAM
Used for general data storage, temporary variables, etc.
Also used for stack (default stack starts at 07H)

🧾 10. Special Function Registers (SFRs)

Located from 80H to FFH
Control and status registers for:
- Timers, Serial, I/O, Interrupts, etc.
Byte-addressable
Some are also bit-addressable (e.g., P0, P1, PSW, IE)

🔁 11. Bank Selection Logic (PSW – Program Status Word)

RS1	RS0	Selected Bank
0	0	Bank 0 (00H–07H)
0	1	Bank 1 (08H–0FH)
1	0	Bank 2 (10H–17H)
1	1	Bank 3 (18H–1FH)

📘 8051 Microcontroller: Stack – Definition and Purpose

🔷 1. Definition and Purpose

The stack is a temporary storage area in internal RAM used to store data during program execution, especially:

Return addresses from subroutines
Temporary register values during interrupts or nested function calls

It operates using the LIFO principle (Last In, First Out).

🔷 2. Role of the Stack in 8051

Helps in quick storage and retrieval of data
Used automatically by CALL/RET, PUSH/POP, interrupts, etc.
Grows upward in memory (toward higher addresses)

🔷 3. Stack Pointer (SP) Register

Attribute	Details
Size	8-bit register
Function	Holds the RAM address of the top of the stack
Default Value	`07H` after reset
Stack Starts	At 08H (next byte after SP)

🔷 4. Stack Operations

Operation	Action
PUSH or CALL	SP is incremented first, then data is stored
POP or RET	Data is retrieved first, then SP is decremented

📌 This means SP always points to the last used location on the stack.

🔷 5. Stack Initialization

After reset:
SP = 07H → stack starts at 08H

You can change SP manually to relocate the stack

assembly

MOV SP, #2FH  ; stack will now start at 30H

🔷 6. Stack Location in RAM

RAM Region	Usage
00H–1FH	Register banks (avoid using for stack)
20H–2FH	Bit-addressable area (avoid stack here too)
30H–7FH	General-purpose RAM (recommended for stack)

✅ Best practice: Set stack above 2FH to avoid conflict with registers and bit-addressable memory

🔷 7. Interaction with RAM Sections

⚠️ If stack overlaps with:

Register banks → R0–R7 data may get corrupted
Bit-addressable RAM → may affect flag bits or control logic

Recommendation: Relocate stack to higher general-purpose RAM section to prevent overwrite.

🔷 8. Illustration / Example

assembly
MOV SP, #2FH     ; Stack starts at 30H

PUSH ACC         ; SP = 30H, ACC saved at 30H → SP = 31H
PUSH B           ; SP = 31H, B saved at 31H → SP = 32H

POP B            ; SP = 32H, B retrieved → SP = 31H
POP ACC          ; SP = 31H, ACC retrieved → SP = 30H

📊 Stack Growth:

java

Initial SP = 2FH
PUSH ACC → SP = 30H (ACC stored)
PUSH B   → SP = 31H (B stored)
POP B    → SP = 31H → 30H
POP ACC  → SP = 30H → 2FH