8051 architecture

DIAGRAM

THEORY

MAP

chat


Formal Definition of 8051 Architecture:

The 8051 microcontroller architecture refers to the internal structure and components of the 8051 microcontroller, which includes the CPU, memory (ROM and RAM), I/O ports, Special Function Registers (SFRs), timers, serial port, and interrupt control — all interconnected through an 8-bit internal data bus.


Exact Topics (No Theory, No Changes):

  1. 1.3 Architecture of 8051
  2. 1.3.1 Central Processing Unit (CPU)
  3. 1.3.2 A and B CPU Registers
  4. 1.3.3 Data Pointer (DPTR)
  5. 1.3.4 The Program Counter
  6. 1.3.5 8051 Flag Bits and the PSW Register
  7. 1.3.6 Special Function Register of 8051

1.3 Architecture of 8051

The 8051 microcontroller includes:

  • CPU,
  • On-chip ROM (4 KB for program memory),
  • On-chip RAM (128 Bytes),
  • Four I/O ports (each 8-bit),
  • Special Function Registers (SFRs),
  • Timer/Counters,
  • Serial port,
  • Interrupt control.

All these units are connected via an 8-bit internal data bus.
The bus is externally accessible via I/O ports if memory or I/O expansion is needed.





1.3.1 Central Processing Unit (CPU)

  • Contains an 8-bit ALU (Arithmetic Logic Unit).
  • Includes key registers:
    • Accumulator (A)
    • B Register,
    • Program Status Word (PSW)
    • Stack Pointer (SP)
    • Program Counter (PC)
    • Data Pointer (DPTR)
  • Performs 8-bit and bit-level operations.

1.3.2 A and B CPU Registers

  • Accumulator (Register A):

    • 8-bit register.
    • Holds operands and results for arithmetic operations.
    • Used in: rotate, parity, zero test.

  • Register B:

    • General-purpose 8-bit register.
    • Mainly used in multiply/divide operations.

1.3.3 Data Pointer (DPTR)

  • A 16-bit register, split into:
    • DPH (High byte)
    • DPL (Low byte)
  • Used to hold a 16-bit memory address.
  • Can be used as:
    • A full 16-bit register, or
    • Two separate 8-bit registers.
  • Important in:
    • Indirect jumps
    • Table look-up
    • External memory/data transfers
  • SFR addresses:
    • DPL – 82H
    • DPH – 83H

1.3.4 Program Counter (PC)

  • A 16-bit register.
  • Holds the address of the next instruction to fetch from program memory.

1.3.5 8051 Flag Bits and PSW Register

  • PSW (Program Status Word) or Flag Register.
  • 8-bit register with the following bits: 
    CY | AC | F0 | RS1 | RS0 | OV | — | P

Flag Descriptions:

  • CY (Carry Flag):

    • Set when there is overflow from bit 7 (also used in subtraction as borrow).

  • AC (Auxiliary Carry Flag):

    • Set when carry from bit 3 to bit 4 occurs (lower to upper nibble).

  • F0 (General Purpose Flag):

    • User-defined for general logic operations.

  • RS1 & RS0 (Register Bank Select bits):

    • Selects one of four register banks:
      RS1 RS0 Register Bank
      0 0 Bank 0 (00H–07H)
      0 1 Bank 1 (08H–0FH)
      1 0 Bank 2 (10H–17H)
      1 1 Bank 3 (18H–1FH)

  • OV (Overflow Flag):

    • Set if result of signed operation is too large.

  • P (Parity Flag):

    • 1 if number of 1s in accumulator is odd,
    • 0 if even.

Example:

  • Adding 9BH and 65H sets:
    • CY = 1, AC = 1, P = 0

1.3.6 Special Function Registers (SFRs)

  • Located from 80H to FFH.
  • Used to control and monitor internal operations.
  • Includes:
    • I/O ports,
    • CPU registers,
    • Timers,
    • Serial port,
    • Interrupt control,
    • Power control.

SFR Properties:

  • Only 21 registers are defined in core 8051.
  • Remaining locations are reserved for future upgrades.
  • Registers are either byte-addressable or bit-addressable.

Important SFRs and Addresses (Table)

Symbol Name Address Notes
ACC Accumulator E0H Bit-addressable
B B Register F0H Bit-addressable
PSW Program Status Word D0H Bit-addressable
SP Stack Pointer 81H
DPL DPTR Low Byte 82H
DPH DPTR High Byte 83H
P0 Port 0 80H Bit-addressable
P1 Port 1 90H Bit-addressable
P2 Port 2 A0H Bit-addressable
P3 Port 3 B0H Bit-addressable
IP Interrupt Priority B8H
IE Interrupt Enable A8H
TMOD Timer Mode Control 89H
TCON Timer Control 88H Bit-addressable
TH0 Timer 0 High Byte 8CH
TL0 Timer 0 Low Byte 8AH
TH1 Timer 1 High Byte 8DH
TL1 Timer 1 Low Byte 8BH
SCON Serial Control 98H Bit-addressable
SBUF Serial Data Buffer 99H
PCON Power Control 87H

* Indicates bit-addressable
+ Indicates 8052-only registers



















Architecture of 8051 Microcontroller

Accumulator:
8-bit register used for arithmetic and logic operations.

B Register:
8-bit general-purpose register.

Program Status Word (PSW):
SFR containing flags to store status information.

Stack Pointer:
8-bit register pointing to the top of the stack.

Data Pointer (DPTR):
16-bit register divided into high byte (DPH) and low byte (DPL). Both have separate addresses in the SFR bank.

Port 0 to Port 3 Latches and Drivers:
Four latch and driver pairs for four on-chip I/O ports. Each latch has an SFR address for communication.

Serial Data Buffer:
Contains two independent registers:

  • Transmit Buffer (parallel-in-serial-out)
  • Receive Buffer (serial-in-parallel-out)
    It is an SFR.

Timer Registers:
Two 16-bit timers:

  • TL0, TH0 for Timer 0
  • TL1, TH1 for Timer 1

Control Registers:
Stores control and status information for interrupts.

Timing and Control Unit:
Generates timing and control signals for internal operations.

Oscillator:
Generates clock signals using a crystal oscillator.

Instruction Register:
Decodes instruction opcodes and signals the timing and control unit for execution.

EPROM and Program Address Register:
Provides on-chip EPROM and internal addressing mechanism.

RAM and RAM Address Register:
Provides 128 bytes of internal RAM with internal addressing.

ALU:
Performs 8-bit arithmetic and logical operations using temporary registers TMP1 and TMP2 (not accessible to users).

SFR Register Bank:
Special Function Registers located from address 80H to FFH.

Full Forms of Abbreviations in 8051 Architecture

AbbreviationFull Form
INTInterrupt
INTEInterrupt Enable
CPUCentral Processing Unit
I/OInput / Output
RAMRandom Access Memory
ROMRead Only Memory
SFRSpecial Function Register
DPHData Pointer High byte
DPLData Pointer Low byte
PCProgram Counter
PSENProgram Store Enable
ALEAddress Latch Enable
XTALCrystal Oscillator
TMODTimer Mode register
THTimer High byte
TLTimer Low byte
TCONTimer Control register
P0, P1, P2, P3Port 0, Port 1, Port 2, Port 3
RXDReceive Data (Serial Input)
TXDTransmit Data (Serial Output)
EAExternal Access Enable
GNDGround
RST / RESETReset Pin
OSCOscillator
ACAccumulator
B RegB Register (used in multiplication/division)